SiC INTRODUTION

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SiC Introdution: Comparison of physical properties; Applications, Advantages and Disadvantages; SiC Arrangement; Introduction to SiC Crystal Growth; SiC specifications; SiC Applications; Introduction to New SiC Technologies

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SiC Introdution

Comparison of physical properties

Applications, Advantages and Disadvantages

SiC
Arrangement

Introduction to SiC Crystal Growth

SiC
Specifications

SiC
Applications

Introduction to New SiC Technologies

Comparison of physical properties

Restricted by its performance, the first-generation semiconductor is not suitable for use in fields such as high temperature, high voltage, high frequency and high power.
Compound semiconductor normally refers to crystalline inorganic compound semiconductor, that is, a compound formed by two or more elements in a determined atomic ratio, with the characteristics of high electron mobility, high band gap, etc., which can be used in high temperature, high voltage, high frequency and other environments.

First generation

GaAs

Second generation

GaN

Third generation

4H-SiC

6H-SiC

3C-SiC

Third generation—SiC

Applications, Advantages and Disadvantages

First-generation semiconductor

Si (silicon) Ge (germanium)

Si (silicon)：Large-scale integrated circuit.
Ge (germanium) ：Low frequency and low voltage, medium power transistors and photodetectors.

Advantages

Mature industrial chain, complete technology and low cost.

Disadvantages

Not resistant to high temperature or high voltage.

Second-generation semiconductor

GaAs (gallium arsenide) InP (indium phosphide)

GaAs (gallium arsenide)：Used for making high-speed, high-frequency, high-power and light-emitting electronic devices.
InP (indium phosphide)：Used in satellite communication, optical communication, positioning system navigation, mobile interconnection and other fields.

Advantages

It has better photoelectric performance, stronger temperature resistance, high frequency and radiation resistance.

Disadvantages

The raw materials are expensive, toxic, easy to pollute the environment, and even carcinogenic.

Third-generation semiconductor

SiC (silicon carbide) GaN (gallium nitride)

SiC (silicon carbide)：Used for photoelectric devices, electronic and power devices and microwave devices.
GaN (gallium nitride)：New energy, wind power, photovoltaic, automobile, consumer electronics, missiles, GPS.

Advantages

Resistant to high temperature, high voltage, high frequency, high power, corrosion, radiation, and large band gap.

Disadvantages

The existing cost is high and the yield is low.

SiC Arrangement

Silicon carbide is a very typical covalent compound, with 88% covalent bonds and only 12% ionic bonds. In any of its crystalline forms, each carbon atom is closely surrounded by four silicon atoms, each of which is also being closely surrounded by four carbon atoms.

From：Peter. J. Wellmann Materials Department 6, Electronic Materials and Energy Technology, Friedrich-Alexander University of Erlangen-Nürnberg, Martensstr. 7, 91058 Erlangen, Germany.

Si-C bilayer crystal stack sequence

Electronic band gap of various SiC types

Introduction to SiC Crystal Growth

Silicon carbide, an inorganic substance with the chemical formula of SiC, is made by smelting quartz sand, petroleum coke (or coal coke), wood chips (salt is required to produce green silicon carbide) and other raw materials in a resistance furnace at high temperature. Silicon carbide also exists in nature as a rare mineral, namely moissanite.

Physical vapor transport

Liquid phase epitaxy

High-temperature chemical vapor deposition

Principle

SiC raw material sublimation and recrystallization(solid state -> gaseous state)

Growth temperature

Above 2000°C

Advantages

Rich experience, large-scale technology under breakthrough

Disadvantages

Low yield and many crystal defects

Principle

Si and C are co-dissolved, and point crystal grows in liquid state(liquid state)

Growth temperature

Above 1800°C

Advantages

Low growth cost and extremely low defect density

Disadvantages

Large-size technology to be broken through

Principle

No solid raw material, crystal growth by feeding gas(gaseous state)

Growth temperature

Above 1600°C

Advantages

High technical plasticity and stable gas supply

Disadvantages

High cost, little experience

SiC specifications

For other specification requirements, please contact us for discussions.

6" n-type specification

8" n-type specification

6" semi-insulated specification

Scratches

Production规范

≤5,Total Length≤Diameter

Dummy规范

Particles

Production规范

≤60(尺寸size≥0.3μm)

Dummy规范

Surface Finish

Production规范

Si-face CMP

Dummy规范

Si-face CMP

Metal contents

Production规范

≤1E11 atom/cm²

Dummy规范

Production规范

Ra≤0.2nm(5μm*5μm)

Dummy规范

Ra≤0.2nm(5μm*5μm)

Warp

Production规范

≤40 um

Dummy规范

≤55 um

Bow

Production规范

-35~35 um

Dummy规范

-45~45 um

LTV

Production规范

≤3(5mm*5mm) um

Dummy规范

≤5(5mm*5mm) um

TTV

Production规范

≤10 um

Dummy规范

≤15 um

Polytype area by diffuse lighting

Production规范

None

Dummy规范

≤30 % area

Micropipe Density

Production规范

≤1 cm²

Dummy规范

≤15 cm²

Secondary flat length

Production规范

None

Dummy规范

None

Primary flat orientation

Production规范

<11-20> ± 5˚

Dummy规范

<11-20> ± 5˚

Primary flat length

Production规范

47.5± 1.5 mm

Dummy规范

47.5± 1.5 mm

Thickness

Production规范

350 μm ± 25 μm

Dummy规范

350 μm ± 25 μm

Diameter

Production规范

150.0mm± 0.25mm

Dummy规范

150.0mm± 0.25mm

Resistivity

Production规范

0.015~0.028

Dummy规范

0.015~0.028

Dopant

Production规范

n-type Nitrogen

Dummy规范

n-type Nitrogen

Surface orientation Off-axis

Production规范

偏 <11-20> 4.0˚ ± 0.5˚

Dummy规范

偏 <11-20> 4.0˚ ± 0.5˚

Polytype

Production规范

Dummy规范

Edge exclusion

Production规范

3mm

Dummy规范

3mm

Scratches

Production规范

Cumulative length ≤200mm

Dummy规范

Surface Finish

Production规范

Si-face CMP

Dummy规范

Si-face CMP

Metal contents

Production规范

≤1E11 atom/cm²

Dummy规范

Production规范

Ra≤0.2nm(5μm*5μm)

Dummy规范

Ra≤0.2nm(5μm*5μm)

Warp

Production规范

≤40 um

Dummy规范

≤70 um

Bow

Production规范

-35~35 um

Dummy规范

-65~65 um

LTV

Production规范

≤10(5mm*5mm) um

Dummy规范

≤15(5mm*5mm) um

TTV

Production规范

≤10 um

Dummy规范

≤20 um

Polytype area by diffuse lighting

Production规范

None permitted

Dummy规范

≤30 % area

Micropipe Density

Production规范

≤2 cm²

Dummy规范

≤50 cm²

Notch Orientation

Production规范

[1-100] ±5°

Dummy规范

[1-100] ±5°

Notch depth

Production规范

1~1.5mm

Dummy规范

1~1.5mm

Thickness

Production规范

TBD

Dummy规范

TBD

Diameter

Production规范

200.0mm± 0.25mm

Dummy规范

200.0mm± 0.25mm

Resistivity

Production规范

0.015~0.028

Dummy规范

Dopant

Production规范

n-type Nitrogen

Dummy规范

n-type Nitrogen

Surface orientation Off-axis

Production规范

偏 <11-20> 4.0˚ ± 0.5˚

Dummy规范

偏 <11-20> 4.0˚ ± 0.5˚

Polytype

Production规范

Dummy规范

Scratches

Production规范

≤5,Total Length≤Diameter

Dummy规范

Particles

Production规范

≤60(尺寸size≥0.3μm)

Dummy规范

Surface Finish

Production规范

Si-face CMP

Dummy规范

Si-face CMP

Metal contents

Production规范

≤1E11 atom/cm²

Dummy规范

Production规范

Ra≤0.2nm(5μm*5μm)

Dummy规范

Ra≤0.2nm(5μm*5μm)

Warp

Production规范

≤40 um

Dummy规范

≤60 um

Bow

Production规范

-25~25 um

Dummy规范

-45~45 um

LTV

Production规范

≤3(5mm*5mm) um

Dummy规范

≤5(5mm*5mm) um

TTV

Production规范

≤10 um

Dummy规范

≤15 um

Polytype area by diffuse lighting

Production规范

None

Dummy规范

≤5 % area

Micropipe Density

Production规范

≤1 cm²

Dummy规范

≤10 cm²

Notch Orientation

Production规范

[1-100] ±5°

Dummy规范

[1-100] ±5°

Notch depth

Production规范

1.0mm +0.25/-0.00mm

Dummy规范

1.0mm +0.25/-0.00mm

Thickness

Production规范

500 μm ± 25 μm

Dummy规范

500 μm ± 25 μm

Diameter

Production规范

150.0mm± 0.2mm

Dummy规范

150.0mm± 0.2mm

Resistivity

Production规范

≥1E8Ω•cm

Dummy规范

(area 75%) ≥1E8Ω·cm

Surface Orientation

Production规范

<0001> ± 0.2˚

Dummy规范

<0001> ± 0.2˚

Polytype

Production规范

Dummy规范

SiC
Applications

xEV Inverter

1400V DC Bus The space occupied by semiconductor products is reduced to 1/3

2750V DC Bus The space occupied by semiconductor products is reduced to 1/5

3Work efficiency can be improved by 5% - 10%

xEV charging infrastructure

1Reduce radiator volume

2Reduce the volume of passive cooling elements

360% reduction in weight and volume

4TOYOTA bZ4X SUV launched in May 2022 will be equipped with a silicon carbide on-board charger and DC converter

xEV OBC/DC-DC on-board power conversion

1Higher energy efficiency

2Reduce the volume of passive cooling elements

3Make the interior more spacious and reduce the weight of the vehicle

xEV Inverter

xEV charging infrastructure

xEV OBC/DC-DC on-board power conversion

Introduction to New SiC Technologies

SICOXS directly bonds polycrystalline SiC and monocrystalline SiC wafers through argon (Ar) beam etching at room temperature, and then separates the bonded monocrystalline SiC, leaving a monocrystalline layer of required thickness on the polycrystalline SiC wafer.

Using this method, two to hundreds of layers can be split from a monocrystalline wafer to produce the same number of bonded SiC wafers. The cost of bonded SiC wafers will be less than half of traditional SiC wafers.

H+ ions are implanted before bonding to a depth corresponding to the desired thickness of the resulting single crystal layer, and then the bonded wafer is annealed to separate the layers. Even with this process, the density of dislocations is similar to that of the pristine wafer, the company reports.

“Kerf-free”dicing

The technical team, which maintains cooperation with the teams with new cutting concepts in the world, participated in the ion cutting and laser cutting tests at the same time in 2015, and confirmed the feasibility of the technologies, which will be introduced for mass production in due time in the future.

Ion cutting

Laser cutting

Ion cutting

Related brands

Hyperion

Related instructions

GTAT, a former major manufacturer of photovoltaic equipment, proposed in 2015 to apply ion cutting technology to the damage-free cutting of silicon carbide materials, with the results confirming that ion cutting is indeed feasible. The research team first implanted 2.3 MeV hydrogen ions into a silicon carbide monocrystalline substrate with a specially designed high-energy ion implanter. The experimental results showed that 2.3 MeV can only penetrate silicon carbide about 30-35 um, which is not operable in the manufacturing process. Therefore, it is necessary to make wafer bonding between the monocrystalline substrate and another supporting material, and then peel off about 30 um of high-quality single crystal film through high-temperature gas expansion. This step can be repeated for the monocrystalline substrate. In theory, 10 times the traditional cutting quantity can be produced, which can greatly reduce the cost of the substrate.
GTAT encountered a financial crisis in 2015, after which it did not continue to carry out relevant technology development until it was acquired by On-Simi for USD 415 million in 2021.

Hyperion™ SiC Wafer

SMART CUT™ PROCESS ADAPTED TO SiC
FULL R&D PILOT LINE RUNNING

Photo source: Soitec’s public information

MAJOR STAGES OF SMART CUT™ SiC

• Donor wafer: Prime quality SiC
• Handle wafer: Low Res SiC
• Conductive bonding interface
• Finishing including CMP & high temp anneal
• Donor wafer re-use for new process cycle

The ion cutting technology introduced by Soitec is to grow an epitaxy layer on a high-quality substrate first, then implant ions at the junction between the epitaxy layer and the substrate, and then perform wafer bonding between the substrate and another piece of silicon carbide low-resistance support material are made into wafer bonding to form an engineering wafer, and finally, the epitaxy layer is separated from the substrate. The substrate has no loss in thickness, and the operation can be repeated. Engineering wafers can be used in the device manufacturing process after bonding.

Laser cutting

Related brands

Related instructions

Source: Infineon’s public information

Siltectra made use of a laser with a specific wavelength to focus on the required depth, and used the high energy of the laser to form material modification. A specially designed polymer material was attached to the substrate to be peeled off, and then the substrate was peeled off by the temperature shock formed by ultra-low temperature.
In 2018, Infineon acquired Siltectra for EUR 124 million. Currently, Infineon’s main efforts are to peel off a substrate of about 150 um after finishing the device manufacturing process, so as to save the cost of substrate.

Siltectra Cold Split Process I

/ Source: Siltectra public information /

Laser process

Creation of a defined layer of modified material in the ingot with µm precision.

Lamination process

Siltectra´s polymer foil is laminated on top of the ingot.

Lift off process

The polymer (elastomer) contracts significantly during a cooling step and a crack is initiated that travels along the laser plane modification.

Finish and reclaim process

The polymer foil is separated from the split wafer and the wafer moves on to subsequent finishing steps. The remaining ingot is reclaimed for the next separation step by a surface conditioning step.

Source: DISCO’s public information

DISCO adopts similar laser cutting principles, but with a higher degree of automation and commercialization. With the acquisition of Siltectra by Infineon, the commercially available laser cutting technologies in the market are dominated by DISCO’s KABRA. It is known that several enterprises have adopted relevant technologies.

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